1. Field of the Invention
This relates generally to MOS devices and fabrication methods therefor and, more particularly, to MOS devices having ion-implanted regions and fabrication methods therefor.
2. Description of the Prior Art
In the past, read-only memories (ROM's) have been implemented in a variety of integrated circuit technology. With the advent of large-scale integrated (LSI) circuits in the MOS format, most prior art ROM's have utilized the N-channel conductivity type devices as opposed to P-channel conductivity type devices because of the increased speed performance possible with the former.
There remains an unfulfilled need for integrated circuit ROM's of lower power consumption. On a theoretical basis, at least, this need may be filled by complementary MOS device ROMs. However, the N-channel device configurations used heretofore in MOS LSI circuits are not viable for the achievement of high density in a row-column array organization of a typical memory.
In order to achieve high density, MOS integrated circuit logic or memory operates at least internally with very low currents in order to achieve small device sizes. The overall size of the integrated circuit, however, is determined not only by the device sizes but also by their packing density. If very low current devices are placed extremely close to each other, the possibility for interaction due to common conduction paths is increased. While there are many known techniques for minimizing or virtually eliminating inter-device interactions which result in false signals, these known techniques consume excessive space in a memory array and, hence, increase the size of the circuit and decrease the yield.